T1/E1 System Synchronizer

Description The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratu

文件：453.05 Kbytes 页数：29 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1/OC3 System Synchronizer

Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu

文件：120.69 Kbytes 页数：30 Pages

MITEL

T1/E1/OC3 System Synchronizer

Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu

文件：120.69 Kbytes 页数：30 Pages

MITEL

T1/E1/OC3 System Synchronizer

Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu

文件：120.69 Kbytes 页数：30 Pages

MITEL

T1/E1/OC3 System Synchronizer

Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are

文件：495.37 Kbytes 页数：34 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1/OC3 System Synchronizer

Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are

文件：495.37 Kbytes 页数：34 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1 System Synchronizer with Holdover

Description The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connect

文件：508.51 Kbytes 页数：34 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1 System Synchronizer with Holdover

Description The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connect

文件：508.51 Kbytes 页数：34 Pages

ZARLINK

Zarlink Semiconductor Inc

Multi-Channel ATM AAL1 SAR

Description The MT90500 Multi-Channel AAL1 SAR is a highly integrated solution which allows systems based on a telecom bus to be interfaced to ATM networks using ATM Adaptation Layer 1 (AAL1), ATM Adaptation Layer 5 (AAL5) and ATM Adaptation Layer 0 (AAL0). The MT90500 can be connected directly t

文件：514.21 Kbytes 页数：159 Pages

MITEL

Multi-Channel ATM AAL1 SAR

Description The MT90500 Multi-Channel AAL1 SAR is a highly integrated solution which allows systems based on a telecom bus to be interfaced to ATM networks using ATM Adaptation Layer 1 (AAL1), ATM Adaptation Layer 5 (AAL5) and ATM Adaptation Layer 0 (AAL0). The MT90500 can be connected directly t

文件：514.21 Kbytes 页数：159 Pages

MITEL