T1/E1/OC3 System Synchronizer

Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are

文件：495.37 Kbytes 页数：34 Pages

ZARLINK

Zarlink Semiconductor Inc

Dual reference frequency selectable 3.3V Digital PLL with multiple clock outputs for T1/E1 (ITU-T G.812 type IV), Stratum( 3, 4, 4E) and STS-3/OC3 systems

Microchip

微芯科技

T1/E1/OC3 System Synchronizer

Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are

文件：495.37 Kbytes 页数：34 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1/OC3 System Synchronizer

Description\nThe MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing\nand synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links.\nThe MT9045 generates ST-BUS clock and framing signals that are phase lo • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces\n• Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces\n• Supports ITU-T G.812 Type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces\n• Supports ETSI E;

Microchip

微芯科技

Package：48-BSSOP（0.295"，7.50mm 宽）；包装：卷带（TR） 功能：数字锁相环 类别：集成电路（IC） 电信 描述：IC TELECOM INTERFACE 48SSOP

Microchip

微芯科技

Package：48-BSSOP（0.295"，7.50mm 宽）；包装：卷带（TR） 功能：数字锁相环 类别：集成电路（IC） 电信 描述：IC TELECOM INTERFACE 48SSOP

Microchip

微芯科技