MT9045AN

T1/E1/OC3 System Synchronizer; • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces\n• Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces\n• Supports ITU-T G.812 Type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces\n• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces\n• Selectable 19.44 MHz, 1.544MHz, 2.048MHz or 8kHz input reference signals\n• Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals\n• Provides 5 styles of 8 KHz framing pulses\n• Holdover frequency accuracy of 0.05 PPM\n• Holdover indication\n• Attenuates wander from 1.9Hz\n• Fast lock mode\n• Provides Time Interval Error (TIE) correction\n• Accepts reference inputs from two independent sources\n• JTAG Boundary ScanApplications\n• Synchronization and timing control for multitrunk T1,E1 and STS-3/OC3 systems\n• ST-BUS clock and frame pulse sources;

Description\nThe MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing\nand synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links.\nThe MT9045 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz,\n1.544MHz, or 8kHz input reference.

MT9045AN

T1/E1/OC3 System Synchronizer

Description TheMT9045T1/E1/OC3SystemSynchronizercontainsadigitalphase-lockedloop(DPLL),whichprovidestiming andsynchronizationsignalsformultitrunkT1andE1primaryratetransmissionlinksandSTS-3/OC3links. TheMT9045generatesST-BUSclockandframingsignalsthatare

MT9045AN1

Package：48-BSSOP（0.295"，7.50mm 宽）；包装：卷带（TR） 功能：数字锁相环 类别：集成电路（IC） 电信 描述：IC TELECOM INTERFACE 48SSOP

MT9045ANR1

Package：48-BSSOP（0.295"，7.50mm 宽）；包装：卷带（TR） 功能：数字锁相环 类别：集成电路（IC） 电信 描述：IC TELECOM INTERFACE 48SSOP

MT9046AN

ZARLINK
SSOP