4/8/16 Port IMA/TC PHY Device

Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat

文件：895.31 Kbytes 页数：55 Pages

ZARLINK

Zarlink Semiconductor Inc

4/8/16 Port IMA/TC PHY Device

Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat

文件：895.31 Kbytes 页数：55 Pages

ZARLINK

Zarlink Semiconductor Inc

4/8/16 Port IMA/TC PHY Device

Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat

文件：895.31 Kbytes 页数：55 Pages

ZARLINK

Zarlink Semiconductor Inc

4/8/16 Port IMA/TC PHY Device

Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat

文件：895.31 Kbytes 页数：55 Pages

ZARLINK

Zarlink Semiconductor Inc

4/8/16 Port IMA/TC PHY Device

Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat

文件：895.31 Kbytes 页数：55 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1 Synchronizer

Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces

文件：424.09 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

文件：650.4 Kbytes 页数：38 Pages

ZARLINK

Zarlink Semiconductor Inc

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

文件：650.4 Kbytes 页数：38 Pages

ZARLINK

Zarlink Semiconductor Inc

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

文件：650.4 Kbytes 页数：38 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1 Synchronizer

Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces

文件：424.09 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc