MT9046集成电路（IC）的电信规格书PDF中文资料

描述 Description

The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connectivity during temporary synchronization interruptions.

特性 Features

• Supports AT&T TR62411 and Bellcore GR-1244- CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces

• Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8kHz input reference signals

• Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals

• Provides 5 styles of 8 KHz framing pulses

• Holdover frequency accuracy of 0.2 PPM

• Holdover indication

• Attenuates wander from 1.9 Hz

• Fast lock mode

• Provides Time Interval Error (TIE) correction

• Accepts reference inputs from two independent sources

• JTAG Boundary Scan

Applications

• Synchronization and timing control for Customer Premises Equipment (CPE)

• ST-BUS clock and frame pulse sources