MT9042集成电路（IC）的电信规格书PDF中文资料

描述 Description

The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz, or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET® T1.5) and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz.

特性 Features

• Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1)

• Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference

• Provides Time Interval Error (TIE) correction to suppress input reference rearrangement transients

• Typical unfiltered intrinsic output jitter is 0.013 UI peak-to-peak

• Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz

• Low power CMOS technology

Applications

• Synchronization and timing control for T1 and E1 digital transmission links

• ST-BUS clock and frame pulse sources

• Primary Trunk Rate Converters