Triple 3-lnput AND Gate High-Performance silicon-gate CMOS

The MC74HC11 is identical in pinout to the LS11. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2

文件：140.03 Kbytes 页数：4 Pages

Motorola

摩托罗拉

Universal Digital Loop Transceiver (UDLT-3) Evaluation Module

Application Circuit At the frequencies of interest (128 kHz and 256 kHz), ordinary telephone wire has a characteristic impedance of about 110 W. In the schematic above, loading resistors R19–22 between LO1 and LO2 and the Tx windings of the transformer are set to 110 W. The series combination o

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恩XP

Triple 3-Input AND Gate

恩XP

Dual J-K Flip-Flop with Set and Reset High?밣erformance Silicon?밎ate CMOS

The MC74HC112 is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip–flop is negative–edge clocked and has active–low asynchronous Set and Reset inputs. The HC112 is identical in f

文件：214.31 Kbytes 页数：6 Pages

Motorola

摩托罗拉

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体