Dual J-K Flip-Flop with Set and Reset High?밣erformance Silicon?밎ate CMOS

The MC74HC112 is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip–flop is negative–edge clocked and has active–low asynchronous Set and Reset inputs. The HC112 is identical in f

文件：214.31 Kbytes 页数：6 Pages

Motorola

摩托罗拉

Dual J-K Flip-Flop with Set and Reset

文件：138.96 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset

恩XP

恩智浦

Dual J-K Flip-Flop with Set and Reset

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安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in

文件：181.12 Kbytes 页数：8 Pages

ONSEMI

安森美半导体