12-BIT PARITY GENERATOR/CHECKER

The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The 100 Series contains temperature compensation. • Provides Odd-HIGH Parity of 12 Inputs • Shiftable Output Register with

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2-BIT 8:1 MULTIPLEXER

Description The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs (SEL0, 1, 2) control which one of the eight data inputs (A0 − A7, B0 − B7) is propagated to the output. The 100 Series contains temperature compensation. Features •

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16:1 MULTIPLEXER

Description The MC10E/100E164 is a 16:1 multiplexer with a differential output. The select inputs (SEL0, 1, 2, 3 ) control which one of the sixteen data inputs (A0 − A15) is propagated to the output. Special attention to the design layout results in a typical skew between the 16 inputs of only 5

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DUAL ECL OUTPUT COMPARATOR WITH LATCH

The MC10E1651 is fabricated using ON Semiconductor’s advanced MOSAIC III™ process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10 KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The devic

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DUAL ECL OUTPUT COMPARATOR WITH LATCH

The MC10E1652 is fabricated using ON Semiconductor’s advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is available in both a 16-pin DIP and a 20-pin surface mount package. However, the MC10E1652 provides user programmable hysteresis. Features •

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9-BIT MAGNITUDE COMPARATOR

Description The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation Features • 1100 ps Max. A = B • PECL Mode Operating Range:

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6-BIT 2:1 MUX-REGISTER

Description The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (

文件：105.97 Kbytes 页数：4 Pages

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5V ECL 12-Bit Parity Generator/Checker

文件：191.99 Kbytes 页数：8 Pages

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5V ECL 12-Bit Parity Generator/Checker

文件：191.99 Kbytes 页数：8 Pages

ONSEMI

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5V ECL 12-Bit Parity Generator/Checker

文件：191.99 Kbytes 页数：8 Pages

ONSEMI

安森美半导体