MC10E1652

DUAL ECL OUTPUT COMPARATOR WITH LATCH

TheMC10E1652isfabricatedusingONSemiconductor’sadvancedMOSAICIIIprocessandisoutputcompatiblewith10Hlogicdevices.Inaddition,thedeviceisavailableinbotha16-pinDIPanda20-pinsurfacemountpackage.However,theMC10E1652providesuserprogrammablehysteresis. Features •

MC10E1652

MC10E1652: Comparator, Dual, ECL Output with Latch; Typical 3.0 dB Bandwidth > 1.0 GHz\nTypical V to Q Propagation Delay of 775 ps\nTypical Output Rise/Fall of 350 ps\nCommon Mode Range -2.0 V to +3.0 V\nIndividual Latch Enables\nDifferential Outputs\nOperating Mode: VCC = 5.0 V, VEE = -5.2 V\nProgrammable Input Hysteresis\nNo Internal Input Pulldown Resistors\nESD Protection: > 2 KV HBM, > 100 V MM\nMeets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test\nMoisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D\nFlammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34\nTransistor Count = 85 devices\n;

The MC10E1652 comparator is fabricated using ON Semiconductor's advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is available in both a 16-pin DIP and a 20-pin surface mount package. However, the MC10E1652 provides user programmable hysteresis. The latch enable (LENabar and LENbbar) input pins operate from standard ECL 10H logic levels. When the latch enable is at a logic high level, the MC10E1652 acts as a comparator; hence, Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Qbar is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state, providing the latch enable setup and hold time constraints are met. The level of input hysteresis is controlled by applying a bias voltage to the HYS pin. The 100 Series contains temperature compensation.

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