MC10E1652数据手册集成电路（IC）的比较器规格书PDF

描述 Description

The MC10E1652 comparator is fabricated using ON Semiconductor's advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is available in both a 16-pin DIP and a 20-pin surface mount package. However, the MC10E1652 provides user programmable hysteresis. The latch enable (LENabar and LENbbar) input pins operate from standard ECL 10H logic levels. When the latch enable is at a logic high level, the MC10E1652 acts as a comparator; hence, Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Qbar is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state, providing the latch enable setup and hold time constraints are met. The level of input hysteresis is controlled by applying a bias voltage to the HYS pin. The 100 Series contains temperature compensation.

特性 Features

Typical 3.0 dB Bandwidth > 1.0 GHz
Typical V to Q Propagation Delay of 775 ps
Typical Output Rise/Fall of 350 ps
Common Mode Range -2.0 V to +3.0 V
Individual Latch Enables
Differential Outputs
Operating Mode: VCC = 5.0 V, VEE = -5.2 V
Programmable Input Hysteresis
No Internal Input Pulldown Resistors
ESD Protection: > 2 KV HBM, > 100 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34
Transistor Count = 85 devices

简介

MC10E1652属于集成电路（IC）的比较器。由制造生产的MC10E1652比较器逻辑比较器系列产品用于根据以数字格式表示的信息比较结果来生成输出；身份型比较器指示两个输入是否相同，幅度型比较器还指示两个输入不相同时哪个较大。它们不同于比较两个模拟输入幅度的器件，后者称为线性比较器且单独分类。