MC10E131中文资料ECL 4-Bit D Flip-Flop数据手册ONSEMI规格书

描述 Description

The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CEbar) inputs for clocking. Common clocking is achieved by holding the CEbar inputs LOW and using CC to clock all four flip-flops. In this case, the CEbar inputs perform the function of controlling the common clock, to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CEbar are LOW, and transfers to the slave when either CC or CEbar (or both) go HIGH.The 100 Series contains temperature compensation.

特性 Features

• 1100MHz Min. Toggle Frequency
• Differential Outputs
• Individual and Common Clocks
• Individual Resets (asynchronous)
• Paired Sets (asynchronous)
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• 75kW Input Pulldown Resistors
• NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
• Internal Input Pulldown Resistors
• Metastability Time Constant is 200 ps.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• ESD Protection: > 2 KV HBM, > 200 V MM
• Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34
• Transistor Count = 240 devices
• Pb-Free Packages are Available

简介

MC10E131属于集成电路（IC）的触发器。由制造生产的MC10E131触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。