MC10E1651中文资料MC10E1651: Comparator, Dual, ECL Output, with Latch数据手册ONSEMI规格书

描述 Description

The MC10E1651 comparator is functionally and pin-for-pin compatible with the MC1651 in the MECL III family, but is fabricated using the advanced MOSAIC III process. The MC10E1651 comparator incorporates a fixed level of input hysteresis as well as output compatibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. The latch enable (LENabar and LENbbar) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a comparator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Qbar is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met.The 100 series contains temperature compensation.

特性 Features

Typical 3.0 dB Bandwidth > 1.0 GHz
Typical V to Q Propagation Delay of 775 ps
Typical Output Rise/Fall of 350 ps
Common Mode Range -2.0 V to +3.0 V
Individual Latch Enables
Differential Outputs
28mV Input Hysteresis
Operating Mode: VCC = 5.0 V, VEE = -5.2 V
No Internal Input Pulldown Resistors
ESD Protection: > 2 KV HBM, > 100 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34
Transistor Count = 85 devices

简介

MC10E1651属于集成电路（IC）的比较器。由制造生产的MC10E1651比较器逻辑比较器系列产品用于根据以数字格式表示的信息比较结果来生成输出；身份型比较器指示两个输入是否相同，幅度型比较器还指示两个输入不相同时哪个较大。它们不同于比较两个模拟输入幅度的器件，后者称为线性比较器且单独分类。