6-BIT 2:1 MUX-REGISTER

Description The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (

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5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes 页数：8 Pages

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5V ECL 6?륛it 2:1 MUX?륱egiste

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5.0 V ECL 6-Bit 2:1 Mux-Register

The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchr • 1000MHz Min. Operating Frequency\n• 800ps Max. Clock to Output\n• Single-Ended Outputs\n• Asynchronous Master Resets\n• DualClocks\n• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\n• Internal Input Pulldown Resist;

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安森美半导体

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes 页数：8 Pages

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安森美半导体

5V ECL 6?륛it 2:1 MUX?륱egiste

文件：156.39 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes 页数：8 Pages

ONSEMI

安森美半导体