Quad Latch

Quad Latch The MC10168 is a Quad Latch with common clocking to all four latches. Separate output enabling gates are provided for each latch, allowing direct wiring to a bus. When the clock is high, outputs will follow the D inputs. Information is latched on the negative–going transition of the cl

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92-Bit Parity Geverator/Checker

9+2-Bit Parity Generator/Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays. The Control Input

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Motorola

摩托罗拉

Dual Binary to 1-4 Decoder(Low)

The MC10171 is a binary coded 2 line to dual 4 line decoder with selected outputs low. With either E0 or E1 high, the corresponding selected 4 outputs are high. The common enable E, when high, forces all outputs high. • PD = 325 mW typ/pkg (No Load) • tpd = 4.0 ns typ • tr, tf = 2.0 ns typ

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Dual Binary to 1-4 Decoder(Low)

The MC10171 is a binary coded 2 line to dual 4 line decoder with selected outputs low. With either E0 or E1 high, the corresponding selected 4 outputs are high. The common enable E, when high, forces all outputs high. • PD = 325 mW typ/pkg (No Load) • tpd = 4.0 ns typ • tr, tf = 2.0 ns typ

文件：110.49 Kbytes 页数：5 Pages

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Dual Binary to 1-4 Decoder(Low)

The MC10171 is a binary coded 2 line to dual 4 line decoder with selected outputs low. With either E0 or E1 high, the corresponding selected 4 outputs are high. The common enable E, when high, forces all outputs high. • PD = 325 mW typ/pkg (No Load) • tpd = 4.0 ns typ • tr, tf = 2.0 ns typ

文件：110.49 Kbytes 页数：5 Pages

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Dual Binary to 1-4 Decoder(Low)

The MC10171 is a binary coded 2 line to dual 4 line decoder with selected outputs low. With either E0 or E1 high, the corresponding selected 4 outputs are high. The common enable E, when high, forces all outputs high. • PD = 325 mW typ/pkg (No Load) • tpd = 4.0 ns typ • tr, tf = 2.0 ns typ

文件：110.49 Kbytes 页数：5 Pages

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Dual Binary to 1-4 Decoder(High)

The MC10172 is a binary-coded 2 line to dual 4 line decoder with selected outputs high. With either E0 or E1 low, the corresponding selected 4 outputs are low. The common enable E, when high, forces all outputs low. PD = 325 mW typ/pkg (No Load) tpd = 4.0 ns typ tr, tf = 2.0 ns typ

文件：117.35 Kbytes 页数：5 Pages

Motorola

摩托罗拉

Quad 2-Input Multiplexer/Latch

Quad 2-Input Multiplexer/Latch The MC10173 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data inputs D00, D10, D20, and D30 and a low (L) level enables dat

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Dual 4 to 1 Multiplexer

The MC10174 is a high speed dual channel multiplexer with output enable capability. The select inputs determine one of four active data inputs for each multiplexer. An output enable forces both outputs low when in the high state. • PD = 305 mW typ/pkg (No Load) • tpd = 3.5 ns typ (Dta to ou

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Dual 4 to 1 Multiplexer

The MC10174 is a high speed dual channel multiplexer with output enable capability. The select inputs determine one of four active data inputs for each multiplexer. An output enable forces both outputs low when in the high state. • PD = 305 mW typ/pkg (No Load) • tpd = 3.5 ns typ (Dta to ou

文件：110.45 Kbytes 页数：4 Pages

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