3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

文件：145.03 Kbytes 页数：10 Pages

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3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

文件：145.03 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

文件：145.03 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

文件：145.03 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

文件：145.03 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

文件：145.03 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

文件：145.03 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

1:4 첨1/첨2 ECL/PECL Clock Fanout Buffer

Description The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device offers two outputs at ÷1 of the input frequency, and two outputs at ÷2 of the input frequency. The Low Output−Output Skew of the device makes it ideal for distributing 1x and 1/2x frequency synchronous signals. Fea

文件：72.19 Kbytes 页数：3 Pages

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첨2, 첨4/6 Clock Generation Chip

Description The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differen

文件：128.009 Kbytes 页数：5 Pages

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3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

文件：120.76 Kbytes 页数：6 Pages

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安森美半导体