2.5V / 3.3V ECL 2-Input Differential AND/NAND

Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applicat

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2.5V / 3.3V ECL 2-Input Differential AND/NAND

Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applicat

文件：104.95 Kbytes 页数：9 Pages

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2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single−ended CLK input operation is limited to a V

文件：134.24 Kbytes 页数：10 Pages

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Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when th

文件：131.96 Kbytes 页数：8 Pages

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Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when th

文件：131.96 Kbytes 页数：8 Pages

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Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when th

文件：131.96 Kbytes 页数：8 Pages

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3.3V ECL 1:9 Differential Clock Driver

文件：130.08 Kbytes 页数：8 Pages

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3.3V ECL 1:9 Differential Clock Driver

文件：130.08 Kbytes 页数：8 Pages

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3.3V ECL 1:9 Differential Clock Driver

文件：132.3 Kbytes 页数：8 Pages

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3.3V ECL 1:9 Differential Clock Driver

文件：130.08 Kbytes 页数：8 Pages

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