첨2, 첨4/6 Clock Generation Chip

Description The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differen

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3.3V ECL 첨2, 첨4/6 Clock Generation Chip

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3.3V ECL Clock Generation Chip

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3.3 V ECL ÷·2, ÷·4/6 Clock Generator Chip

The MC100LVEL38 is a low skew w 2, w 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or singl • 50 ps Maximum Output-to-Output Skew\n• Synchronous Enable/Disable\n• Master Reset for Synchronization\n• ESD Protection: >2 KV HBM\n• The 100 Series Contains Temperature Compensation\n• PECL Mode Operating Range: VCC = 3.0 V to 3.8 Vwith VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE =;

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3.3V ECL 첨2, 첨4/6 Clock Generation Chip

文件：123.37 Kbytes 页数：7 Pages

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安森美半导体

3.3V ECL Clock Generation Chip

文件：242.35 Kbytes 页数：7 Pages

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安森美半导体

3.3V ECL 첨2, 첨4/6 Clock Generation Chip

文件：123.37 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2, 첨4/6 Clock Generation Chip

文件：123.37 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

3.3V ECL Clock Generation Chip

文件：242.35 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2, 첨4/6 Clock Generation Chip

文件：123.37 Kbytes 页数：7 Pages

ONSEMI

安森美半导体