Description

The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Features

• 50 ps Typical Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• 1.5 GHz Toggle Frequency

• The 100 Series Contains Temperature Compensation.

• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V

• Open Input Default State

• LVDS Input Compatible

• Pb−Free Packages are Available

MC100LVEL34DG属于集成电路（IC） > 时钟发生器，PLL，频率合成器。安森美半导体公司制造生产的MC100LVEL34DG时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。