MC100EP809数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The MC100EP809 is a low skew 2:1:9 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state.The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration. To ensure that tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used.If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.Designers can take advantage of the EP809's performance to distribute low skew clocks across the backplane of the board.HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair.

特性 Features

• 100 ps Typical Device-to-Device Skew
• 15 ps Typical Within Device Skew
• HSTL Compatible Outputs Drive 50Ω to Ground with no Offset Voltage
• Maximum Frequency > 750 MHz
• 850 ps Typical Propagation Delay
• Fully Compatible with Micrel SY89809L
• PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V
• Open Input Default State
• Pb-Free Packages are Available

应用 Application

• Clock distribution

简介

MC100EP809属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的MC100EP809时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。