MC100EP35中文资料ECL JK 触发器数据手册ONSEMI规格书

描述 Description

The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.The 100 Series contains temperature compensation.

特性 Features

• 410 ps Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range:VCC = 0 V with VEE = -3.0V to -5.5V
• Open Input Default State
• Q Output will default LOW with inputs open or at VEE
• Pb-Free Packages are Available

应用 Application

• Using ECL Logic technologies for reducing system clock skew over the alternative CMOS and TTL technologies.

简介

MC100EP35属于集成电路（IC）的触发器。由制造生产的MC100EP35触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。