3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

文件：75.86 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

文件：137.79 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

时钟驱动器，2:1:9 差分 HSTL / PECL 至 HSTL，3.3 V

The MC100EP809 is a low skew 2:1:9 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew sign • 100 ps Typical Device-to-Device Skew\n• 15 ps Typical Within Device Skew\n• HSTL Compatible Outputs Drive 50Ω to Ground with no Offset Voltage\n• Maximum Frequency > 750 MHz\n• 850 ps Typical Propagation Delay\n• Fully Compatible with Micrel SY89809L\n• PECL and HSTL Mode Operating Range: VCCI = 3;

ONSEMI

安森美半导体

3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

文件：137.79 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Differentia HSTL/PECL/LVDS to HSTL Clock Driver

文件：112.19 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

文件：75.86 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

文件：137.79 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

文件：137.79 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Differentia HSTL/PECL/LVDS to HSTL Clock Driver

文件：112.19 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

文件：137.79 Kbytes 页数：9 Pages

ONSEMI

安森美半导体