MC100EP196中文资料3.3 V ECL Programmable Delay Chip数据手册ONSEMI规格书

描述 Description

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.

特性 Features

• Maximum Frequency > 1.2 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
• Open Input Default State
• Safety Clamp on Inputs
• A Logic High on the ENbar Pin Will Force Q to Logic Low
• D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
• VBB Output Reference Voltage
• Pb-Free Packages are Available

简介

MC100EP196属于集成电路（IC）的延迟线。由制造生产的MC100EP196延迟线时钟延迟线产品族中的产品属于数字器件，用于在数字信号中引入时间延迟，以便将提交给器件输入的信号跃迁，经过某一已知时间之后在输出端复现。它们常用于高速数字系统，以校正或补偿不同信号路径之间的信号传播时间的偏差。这些器件可用于产生固定、可选或可变持续时间的延迟。