MC100EP196

3.3 V ECL Programmable Delay Chip; • Maximum Frequency > 1.2 GHz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• A Logic High on the ENbar Pin Will Force Q to Logic Low\n• D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs\n• VBB Output Reference Voltage\n• Pb-Free Packages are Available\n;

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.

MC100EP196

3.3V ECL Programmable Delay Chip with FTUNE

MC100EP196

3.3V ECL Programmable Delay Chip with FTUNE

MC100EP196_06

3.3V ECL Programmable Delay Chip with FTUNE

MC100EP196_14

3.3V ECL Programmable Delay Chip with FTUNE

MC100EP196A

3.3 V ECL Programmable Delay Chip

MC100EP196AMNG

3.3 V ECL Programmable Delay Chip

MC100EP196AMNR4G

3.3 V ECL Programmable Delay Chip

MC100EP196B

3.3 V ECL Programmable Delay Chip With FTUNE

MC100EP196B_14

ECL Programmable Delay Chip With FTUNE