3.3V ECL Programmable Delay Chip with FTUNE

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3.3V ECL Programmable Delay Chip with FTUNE

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3.3 V ECL Programmable Delay Chip

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE • Maximum Frequency > 1.2 GHz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• A Logic High on the ENbar Pin Will Force Q to Logic Low\n• D[0:10] Can ;

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3.3V ECL Programmable Delay Chip with FTUNE

文件：215.19 Kbytes 页数：18 Pages

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3.3V ECL Programmable Delay Chip with FTUNE

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3.3 V ECL Programmable Delay Chip

文件：158.22 Kbytes 页数：18 Pages

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3.3 V ECL Programmable Delay Chip

文件：158.22 Kbytes 页数：18 Pages

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3.3 V ECL Programmable Delay Chip

文件：158.22 Kbytes 页数：18 Pages

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3.3 V ECL Programmable Delay Chip With FTUNE

文件：232 Kbytes 页数：18 Pages

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ECL Programmable Delay Chip With FTUNE

文件：165.62 Kbytes 页数：18 Pages

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