MC100EP016A数据手册集成电路（IC）的计数器除法器规格书PDF

描述 Description

The MC100EP016A is a high-speed synchronous, presettable, cascadeable 8-bit binarycounter. Architecture and operation are the same as the MC100E016 in the ECLinPS family.The counter features internal feedback to TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TCbar feedback is disabled, and counting proceeds continuously, with TCbar going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. COUT and COUTbar provide differential outputs from a single, non-cascaded counter or divider application. COUT and COUTbar should not be used in cascade configuration. Only TCbar should be used for a counter or divider cascade chain output. A differential clock input has also been added to improve performance. The 100 Series contains temperature compensation.

特性 Features

• 550 ps Typical Propagation Delay
• Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
• PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
• Open Input Default State
• Safety Clamp on Clock Inputs
• Internal TCbar Feedback (Gated)
• Addition of COUT and COUTbar
• 8-bit
• Differential Clock Input
• VBB Output
• Fully Synchronous Counting and TCbar Generation
• Asynchronous Master Reset
• Pb-Free Packages are Available

应用 Application

• Hi-Speed Binary Counting

简介

MC100EP016A属于集成电路（IC）的计数器除法器。由制造生产的MC100EP016A计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。