MC100EL35中文资料MC100EL35: ECL JK Flip-Flop数据手册ONSEMI规格书

描述 Description

The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.

特性 Features

525ps Propagation Delay
2.2GHz Toggle Frequency
ESD Protection: > 1 kV HBM, > 100 V MM
PECL Mode Operating Range: VCC= 4.2 V to 5.7 with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V
Internal Input Pulldown Resistors on J, K, CLK, and R
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94V-0 @ 0.125 in, Oxygen Index: 28 to 34
Transistor Count = 81 devices
Pb-Free Packages are Available

应用 Application

Timing Circuits

简介

MC100EL35属于集成电路（IC）的触发器。由制造生产的MC100EL35触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。