MC100EL34中文资料5.0 V ECL ÷2, ÷4, ÷8 Clock Generation Chip数据手册ONSEMI规格书

描述 Description

The MC10/100EL34 is a low skew divide by 2, divide by 4, divide by 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the input of the EL34 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system.The 100 Series contains temperature compensation.

特性 Features

• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
• Internal Input Pulldown Resistors on CLK(s), ENbar, and MR
• Pb-Free Packages are Available

简介

MC100EL34属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的MC100EL34时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。