JK Flip-Flop

Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic

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5V ECL JK Flip-Flop

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MC100EL35: ECL JK Flip-Flop

The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. 525ps Propagation Delay\n2.2GHz Toggle Frequency\nESD Protection: > 1 kV HBM, > 100 V MM\nPECL Mode Operating Range: VCC= 4.2 V to 5.7 with VEE= 0 V\nNECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V\nInternal Input Pulldown Resistors on J, K, CLK, and R\nMeets or Exceeds JEDEC Spec EIA;

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5V ECL JK Flip-Flop

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Evaluation Board Manual for High Frequency SOIC 8

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5 V ECL JK Flip?륡lop

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安森美半导体

5V ECL JK Flip-Flop

文件：144.93 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL JK Flip-Flop

文件：144.93 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL JK Flip-Flop

文件：144.93 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL JK Flip-Flop

文件：144.93 Kbytes 页数：8 Pages

ONSEMI

安森美半导体