5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

文件：107.22 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

文件：107.22 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

6-BIT 2:1 MUX-LATCH

Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

文件：105.49 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

3-BIT 4:1 MUX-LATCH

Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LE

文件：106.78 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. • Individual Select Controls • 550ps Max. D to Output • 80

文件：99.46 Kbytes 页数：4 Pages

Motorola

摩托罗拉

QUAD 2:1 MULTIPLEXER

Description The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. The 100 Series contains temperature compensation.

文件：99.46 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. • Individual Select Controls • 550ps Max. D to Output • 80

文件：99.46 Kbytes 页数：4 Pages

Motorola

摩托罗拉

QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. • Individual Select Controls • 550ps Max. D to Output • 80

文件：99.46 Kbytes 页数：4 Pages

Motorola

摩托罗拉

5-BIT 2:1 MULTIPLEXER

Description The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input (SEL). The 100 Series contains temperature compensation. Features • 600 ps Max. D to Output • 800 ps Max. SEL to Output • Differential Outputs • One VCC

文件：100.73 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

12-BIT PARITY GENERATOR/CHECKER

The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The 100 Series contains temperature compensation. • Provides Odd-HIGH Parity of 12 Inputs • Shiftable Output Register with

文件：106.47 Kbytes 页数：4 Pages

ONSEMI

安森美半导体