6-BIT 2:1 MUX-LATCH

Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

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安森美半导体

5V ECL 6?묪it 2:1 Mux?묹atch

文件：126.97 Kbytes 页数：8 Pages

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安森美半导体

6-BIT 2:1 MUX-LATCH

ONSEMI

安森美半导体

5V ECL 6?묪it 2:1 Mux?묹atch

文件：126.97 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 6?묪it 2:1 Mux?묹atch

文件：126.97 Kbytes 页数：8 Pages

ONSEMI

安森美半导体