3-BIT 4:1 MUX-LATCH

Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LE

文件：106.78 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

5V ECL 3-Bit 4:1 Mux-Latch

文件：126.9 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 3-Bit 4:1 Mux-Latch

文件：126.9 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

Micrel

麦瑞半导体