5V ECL 3-Bit 4:1 Mux-Latch

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ONSEMI

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3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latche

文件：60.87 Kbytes 页数：4 Pages

Micrel

麦瑞半导体