첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

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安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：69.23 Kbytes 页数：8 Pages

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安森美半导体

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

ONSEMI

安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：69.23 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：69.23 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

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安森美半导体

JK Flip-Flop

Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic

文件：75.53 Kbytes 页数：3 Pages

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安森美半导体

첨2, 첨4/6 Clock Generation Chip

Description The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differen

文件：128.009 Kbytes 页数：5 Pages

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安森美半导体

5V ECL Clock Generation Chip

The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-

文件：160.89 Kbytes 页数：6 Pages

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安森美半导体

5V ECL Clock Generation Chip

The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-

文件：160.89 Kbytes 页数：6 Pages

ONSEMI

安森美半导体