SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER

Reverse Voltage - 40 to 200 Volts Forward Current - 2.0 Amperes FEATURES • Plastic package has Underwriters Laboratory Flammability Classification 94V-O • For surface mounted applications • Low profile package • Built-in strain relief • Metal to silicon rectifier. majority carrier conduc

文件：229.42 Kbytes 页数：2 Pages

SY

顺烨电子

SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER

文件：97.1 Kbytes 页数：2 Pages

PANJIT

強茂

1.0A SURFACE MOUNT SCHOTTKY BARRIER DIODE

文件：112.79 Kbytes 页数：2 Pages

ZSELEC

淄博圣诺

丝印：MB28F；Package：MBF；2A SURFACE MOUNT SCHOTTKY BRIDGE

文件：294.1 Kbytes 页数：3 Pages

SKTECHNOLGYSHIKE Electronics

时科广东时科微实业有限公司

Dual 10-bit D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The MB2821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • 20-bit positive-edge triggered register • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitted • Power

文件：112.5 Kbytes 页数：9 Pages

PHI

飞利浦

Dual 10-bit D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The MB2821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • 20-bit positive-edge triggered register • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitted • Power

文件：112.5 Kbytes 页数：9 Pages

PHI

飞利浦

Dual 10-bit buffer/line driver; non-inverting 3-State

DESCRIPTION The MB2827 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The MB2827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Ena

文件：94.21 Kbytes 页数：8 Pages

PHI

飞利浦

Dual 10-bit buffer/line driver; non-inverting 3-State

DESCRIPTION The MB2827 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The MB2827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Ena

文件：94.21 Kbytes 页数：8 Pages

PHI

飞利浦

Dual 10-bit bus interface latch 3-State

DESCRIPTION The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High.

文件：66.1 Kbytes 页数：10 Pages

PHI

飞利浦

Dual 10-bit bus interface latch 3-State

DESCRIPTION The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High.

文件：66.1 Kbytes 页数：10 Pages

PHI

飞利浦