MB2841BB中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity.

The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched.

Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state.

FEATURES

• High speed parallel latches

• Live insertion/extraction permitted

• Extra data width for wide address/data

paths or buses carrying parity

• Power-up 3-State

• Power-up reset

• Ideal where high speed, light loading, or

increased fan-in are required with MOS microprocessors

• Output capability: +64mA/–32mA

• Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17

• ESD protection exceeds 2000V per MIL

STD 883 Method 3015 and 200V per Machine Model