MB2861中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The MB2861 bus transceiver provides high performance bus interface buffering for wide data/address paths of buses carrying parity.

The MB2861 10-bit bus transceiver has NOR-ed transmit and receive output enables for maximum control flexibility.

FEATURES

• Provides high performance bus interface

buffering for wide data/address paths or buses carrying parity

• Buffered control inputs for light loading, or

increased fan-in as required with MOS microprocessors

• Output capability: +64mA/-32mA

• Power-up 3-State

• Live insertion/extraction permitted

• Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17

• ESD protection exceeds 2000 V per MIL

STD 883 Method 3015 and 200 V per Machine Model