8 Mbit 512K x16 3.0V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AW512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This de

文件：124.09 Kbytes 页数：18 Pages

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8 Mbit (512K x16) 3.0V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AW512M is a 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This dev

文件：296.74 Kbytes 页数：19 Pages

STMICROELECTRONICS

意法半导体

8 Mbit (512K x16) 3.0V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AW512M is a 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This dev

文件：296.74 Kbytes 页数：19 Pages

STMICROELECTRONICS

意法半导体

8 Mbit 512K x16 3.0V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AW512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This de

文件：124.09 Kbytes 页数：18 Pages

STMICROELECTRONICS

意法半导体

8 Mbit 512K x16 3.0V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AW512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This de

文件：124.09 Kbytes 页数：18 Pages

STMICROELECTRONICS

意法半导体