LMK04832-SP中文资料Space grade ultra low-Noise JESD204B compliant clock jitter cleaner数据手册TI规格书

描述 Description

The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The LMK04832-SP can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows the LMK04832-SP to provide flexible high performance clocking trees.

The LMK04832-SP comes in a 10.9-mm × 10.9-mm, 64-pin CFP package.

特性 Features

• SMD #5962R1723701VXC
• SEL immune >120 MeV × cm2/mg
• Maximum clock output frequency: 3255 MHz
• 6-GHz external VCO or distribution input
• 54-fs RMS jitter (12 kHz to 20 MHz)
• –157.6-dBc/Hz noise floor
• Ultra-low noise, at 3200 MHz:
• 67-fs RMS jitter (100 Hz to 100 MHz)
• PLL2
• PLL 1/f of –128 dBc/Hz
• Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
• Up to 14 differential device clocks
• Up to 1 buffered VCXO/XO output
• 1-1023 CLKout divider
• 25-ps step analog delay for SYSREF clocks
• Holdover mode with PLL1
• Ambient temperature range: –55 °C to 125 °C