LMK04832-SEP数据手册TI中文资料规格书

描述 Description

The LMK04832-SEP is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees.

特性 Features

• VID#: V62/22612
• Total ionizing dose 30 krad (ELDRS-free)
• SEL immune >43 MeV × cm2/mg
• SEFI immune >43 MeV × cm2/mg

• Ambient temperature range: –55°C to 125°C
• Maximum clock output frequency: 3255 MHz
• Multi-mode: dual PLL, single PLL, and clock distribution
• 6-GHz external VCO or distribution input
• Ultra-low noise, at 2500 MHz:
• 54-fs RMS jitter (12 kHz to 20 MHz)
• 64-fs RMS jitter (100 Hz to 20 MHz)
• –157.6-dBc/Hz noise floor

• Ultra-low noise, at 3200 MHz:
• 61-fs RMS jitter (12 kHz to 20 MHz)
• 67-fs RMS jitter (100 Hz to 100 MHz)
• –156.5-dBc/Hz noise floor

• PLL2
• PLL FOM of –230 dBc/Hz
• PLL 1/f of –128 dBc/Hz
• Phase detector rate up to 320 MHz
• Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz

• Up to 14 differential device clocks
• CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs

• Up to 1 buffered VCXO/XO output
• LVPECL, LVDS, 2xLVCMOS programmable

• 1-1023 CLKOUT divider
• 1-8191 SYSREF divider
• 25-ps step analog delay for SYSREF clocks
• Digital delay and dynamic digital delay for device clocks and SYSREF
• Holdover mode with PLL1
• 0-delay with PLL1 or PLL2