LMK04828-EP数据手册TI中文资料规格书

描述 Description

The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.

特性 Features

• EP Features
• Gold Bondwires
• Temperature Range: –55 to +105 °C
• Lead Finish SnPb

• Maximum Distribution Frequency: 3.2 GHz
• JESD204B Support
• Ultra-Low RMS Jitter
• 88-fs RMS Jitter (12 kHz to 20 MHz)
• 91-fs RMS Jitter (100 Hz to 20 MHz)
• –162.5 dBc/Hz Noise Floor at 245.76 MHz

• Up to 14 Differential Device Clocks From PLL2
• Up to 7 SYSREF Clocks
• Maximum Clock Output Frequency 3.2 GHz
• LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2

• Up to 1 Buffered VCXO/Crystal Output From PLL1
• LVPECL, LVDS, 2xLVCMOS Programmable

• Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
• Dual Loop PLLatinum™ PLL Architecture
• PLL1
• Up to 3 Redundant Input Clocks
• Automatic and Manual Switchover Modes
• Hitless Switching and LOS

• Integrated Low-Noise Crystal Oscillator Circuit
• Holdover Mode When Input Clocks are Lost

• PLL2
• Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
• Phase Detector Rate up to 155 MHz
• OSCin Frequency-Doubler
• Two Integrated Low-Noise VCOs

• 50% Duty Cycle Output Divides, 1 to 32 (Even and Odd)
• Precision Digital Delay, Dynamically Adjustable
• 25-ps Step Analog Delay
• 3.15-V to 3.45-V Operation
• Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)