LMK04821中文资料支持 JESD204B 的超低抖动合成器和抖动消除器数据手册TI规格书

描述 Description

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.

特性 Features

• JEDEC JESD204B Support
• 88 fs RMS Jitter (12 kHz to 20 MHz)
• –162.5 dBc/Hz Noise Floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2
• Maximum Clock Output Frequency 3.1 GHz
• Up to 1 Buffered VCXO/Crystal Output from PLL1
• Dual Loop PLLatinum™ PLL Architecture
• Up to 3 Redundant Input Clocks
• Hitless Switching and LOS
• Integrated Low-Noise Crystal Oscillator Circuit
• PLL2
• Phase Detector Rate up to 155 MHz
• Two Integrated Low-Noise VCOs
• 50% Duty Cycle Output Divides, 1 to 32 (even and odd)
• 25-ps Step Analog Delay
• Industrial Temperature Range: –40 to 85°C
• 3.15-V to 3.45-V Operation
• Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)