LMK04821数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.

特性 Features

• JEDEC JESD204B Support
• Ultra-Low RMS Jitter
• 88 fs RMS Jitter (12 kHz to 20 MHz)
• 91 fs RMS Jitter (100 Hz to 20 MHz)
• –162.5 dBc/Hz Noise Floor at 245.76 MHz

• Up to 14 Differential Device Clocks from PLL2
• Up to 7 SYSREF Clocks
• Maximum Clock Output Frequency 3.1 GHz
• LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2

• Up to 1 Buffered VCXO/Crystal Output from PLL1
• LVPECL, LVDS, 2xLVCMOS Programmable

• Dual Loop PLLatinum™ PLL Architecture
• PLL1
• Up to 3 Redundant Input Clocks
• Automatic and Manual Switch-Over Modes
• Hitless Switching and LOS

• Integrated Low-Noise Crystal Oscillator Circuit
• Holdover Mode When Input Clocks are Lost

• PLL2
• Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
• Phase Detector Rate up to 155 MHz
• OSCin Frequency-Doubler
• Two Integrated Low-Noise VCOs

• 50% Duty Cycle Output Divides, 1 to 32 (even and odd)
• Precision Digital Delay, Dynamically Adjustable
• 25-ps Step Analog Delay
• Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
• Industrial Temperature Range: –40 to 85°C
• Supports 105°C PCB Temperature (Measured at Thermal Pad)
• 3.15-V to 3.45-V Operation
• Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)