丝印：K5C；Package：SOT-323；PNP SURFACE MOUNT TRANSISTOR

Features • Ideally Suited for Automatic Insertion • Epitaxial Planar Die Construction • For Switching, AF Driver and Amplifier Applications • Complementary NPN Types Available (BC817-xxW) • Lead Free By Design/RoHS Compliant (Note 1) • Green Device (Note 2)

文件：363.65 Kbytes 页数：3 Pages

DIODES

美台半导体

丝印：K5C33216；Package：VQFN(RGC)；LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器

丝印：K5C33216；Package：VQFN(RGC)；LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器

丝印：K5C33216；Package：VQFN(RGC)；LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器

丝印：K5C33216；Package：VQFN(RGC)；LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器

丝印：K5C33216；Package：VQFN(RGC)；LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器

丝印：K5C33216；Package：VQFN(RGC)；LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器