丝印：K5B；Package：SOT-323；PNP SURFACE MOUNT TRANSISTOR

Features • Ideally Suited for Automatic Insertion • Epitaxial Planar Die Construction • For Switching, AF Driver and Amplifier Applications • Complementary NPN Types Available (BC817-xxW) • Lead Free By Design/RoHS Compliant (Note 1) • Green Device (Note 2)

文件：363.65 Kbytes 页数：3 Pages

DIODES

美台半导体

丝印：K5B12212；Package：VQFN；LMK5B12212 1-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF) – 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF – 42fs typical/ 60fs maximum RMS jitter at 312.5MHz – 47fs typical/ 65fs maximum RMS jitt

文件：5.65494 Mbytes 页数：97 Pages

TI

德州仪器

丝印：K5B33216；Package：VQFN；LMK5B33216 3-DPLL, 3-APLL, 2-IN, 16-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz • 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programmable D

文件：6.2205 Mbytes 页数：102 Pages

TI

德州仪器

丝印：K5B33216；Package：VQFN；LMK5B33216 3-DPLL, 3-APLL, 2-IN, 16-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz • 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programmable D

文件：6.2205 Mbytes 页数：102 Pages

TI

德州仪器

丝印：K5B33414；Package：VQFN；LMK5B33414 3-DPLL, 3-APLL, 4-IN, 14-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz • 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programmable D

文件：6.4373 Mbytes 页数：102 Pages

TI

德州仪器

丝印：K5B33414；Package：VQFN；LMK5B33414 3-DPLL, 3-APLL, 4-IN, 14-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz • 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programmable D

文件：6.4373 Mbytes 页数：102 Pages

TI

德州仪器