首页>K4H510438C-TLB0>规格书详情
K4H510438C-TLB0中文资料PDF规格书
相关芯片规格书
更多- K4H510438B-TCB0
- K4H510438B-TCA0
- K4H510438B-TCA2
- K4H510438C-TLA0
- K4H510438C-TLA2
- K4H510438C-TCB0
- K4H510438B-TLB0
- K4H510438B-UC/LA2
- K4H510438B-TC/LA2
- K4H510438B-UC/LB3
- K4H510438C-LA2
- K4H510438C-LB0
- K4H510438C-LCC
- K4H510438B-TC/LB3
- K4H510438B-UC/LB0
- K4H510438B-TC/LB0
- K4H510438B-ZC/LCC
- K4H510438B-ZC/LA2
K4H510438C-TLB0规格书详情
Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
产品属性
- 型号:
K4H510438C-TLB0
- 制造商:
SAMSUNG
- 制造商全称:
Samsung semiconductor
- 功能描述:
128Mb DDR SDRAM
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SAMSUNG |
23+ |
TSOP66 |
20000 |
全新原装假一赔十 |
询价 | ||
SAMSUNG/三星 |
22+ |
TSSOP66 |
100000 |
代理渠道/只做原装/可含税 |
询价 | ||
SAMSUNG |
23+ |
TSOP |
20000 |
原厂原装正品现货 |
询价 | ||
SAMSUNG |
23+ |
TSSOP |
1072 |
优势库存 |
询价 | ||
SAMSUNG/三星 |
22+ |
TSSOP66 |
354000 |
询价 | |||
SAMSUNG/三星 |
24+ |
TSOP-66 |
58000 |
全新原厂原装正品现货,可提供技术支持、样品免费! |
询价 | ||
SANSUNG |
21+ |
66TSOP |
35200 |
一级代理/放心采购 |
询价 | ||
SAMSUNG/三星 |
23+ |
NA/ |
122 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
SAMSUNG |
6000 |
面议 |
19 |
DIP/SMD |
询价 | ||
SAMSUNG/三星 |
24+ |
TSOP-66 |
880000 |
明嘉莱只做原装正品现货 |
询价 |