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K4H510438B-TLB0中文资料PDF规格书
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Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
产品属性
- 型号:
K4H510438B-TLB0
- 制造商:
SAMSUNG
- 制造商全称:
Samsung semiconductor
- 功能描述:
128Mb DDR SDRAM
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
23+ |
TSSOP |
50000 |
全新原装正品现货,支持订货 |
询价 | ||
SAMSUNG/三星 |
21+ |
TSSOP |
10000 |
原装现货假一罚十 |
询价 | ||
SAMSUNG |
22+ |
TSOP |
360000 |
进口原装房间现货实库实数 |
询价 | ||
SAMSUNG |
23+ |
TSOP |
20000 |
原厂原装正品现货 |
询价 | ||
SAMSUNG |
21+ |
35200 |
一级代理/放心采购 |
询价 | |||
SAMSANG |
19+ |
TSSOP |
256800 |
原厂代理渠道,每一颗芯片都可追溯原厂; |
询价 | ||
SAMSUNG |
23+ |
TSSOP |
1072 |
优势库存 |
询价 | ||
SAMSUNG/三星 |
23+ |
TSSOP |
20000 |
原装正品 欢迎咨询 |
询价 | ||
SAMSUNG |
22+ |
TSOP |
6980 |
原装现货,可开13%税票 |
询价 | ||
SAMSUNG |
16+ |
TSOP |
5188 |
全新、原装 |
询价 |