丝印：ICS854S006AIL；Low Skew, 1-to-6, Differential-to-LVDS Fanout Buffer

Features ▪ Six differential LVDS outputs ▪ One differential clock input pair ▪ CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL ▪ Maximum output frequency: 1.7GHz ▪ Translates any single-ended input signal to LVDS levels with resistor bias

文件：1.09572 Mbytes 页数：18 Pages

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瑞萨

丝印：ICS854S006AIL；Low Skew, 1-to-6, Differential-to-LVDS Fanout Buffer

Features ▪ Six differential LVDS outputs ▪ One differential clock input pair ▪ CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL ▪ Maximum output frequency: 1.7GHz ▪ Translates any single-ended input signal to LVDS levels with resistor bias

文件：1.09572 Mbytes 页数：18 Pages

RENESAS

瑞萨