丝印：ICS8735AY31LF；Package：LQFP；1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

文件：620.77 Kbytes 页数：22 Pages

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丝印：ICS8735AY31LF；Package：LQFP；1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

文件：610.74 Kbytes 页数：22 Pages

RENESAS

瑞萨

丝印：ICS8735AY31LF；Package：LQFP；1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

文件：620.77 Kbytes 页数：22 Pages

RENESAS

瑞萨

丝印：ICS8735AY31LF；Package：LQFP；1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • V

文件：610.74 Kbytes 页数：22 Pages

RENESAS

瑞萨