丝印：ICS9S0412BIL；Package：TSSOP；4:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 4:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Four selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output fre

文件：1.13242 Mbytes 页数：24 Pages

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丝印：ICS9S0412BIL；Package：TSSOP；4:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 4:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Four selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output fre

文件：1.13242 Mbytes 页数：24 Pages

RENESAS

瑞萨