丝印：ICS8725BM-21LF；Package：SOIC；Differential-To-HSTL Zero Delay Clock Generator

Features • One differential HSTL output pair One differential feedback output pair • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential  input levels: LVPECL, LVDS, HSTL, HCSL, SSTL • Output frequency range: 31.25MHz to 630MHz • Input frequency range:

文件：536.06 Kbytes 页数：16 Pages

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丝印：ICS8725BM-21LF；Package：SOIC；Differential-To-HSTL Zero Delay Clock Generator

Features • One differential HSTL output pair One differential feedback output pair • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential  input levels: LVPECL, LVDS, HSTL, HCSL, SSTL • Output frequency range: 31.25MHz to 630MHz • Input frequency range:

文件：536.06 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS8725BM-21LF；Package：SOIC；Differential-To-HSTL Zero Delay Clock Generator

Features • One differential HSTL output pair One differential feedback output pair • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential  input levels: LVPECL, LVDS, HSTL, HCSL, SSTL • Output frequency range: 31.25MHz to 630MHz • Input frequency range:

文件：536.06 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS8725BM-21LF；Package：SOIC；Differential-To-HSTL Zero Delay Clock Generator

Features • One differential HSTL output pair One differential feedback output pair • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential  input levels: LVPECL, LVDS, HSTL, HCSL, SSTL • Output frequency range: 31.25MHz to 630MHz • Input frequency range:

文件：536.06 Kbytes 页数：16 Pages

RENESAS

瑞萨