Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 页数：5 Pages

PHI

飞利浦

Dual JK flip-flop

General description The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH async

文件：83.13 Kbytes 页数：13 Pages

恩XP

Dual JK flip-flop

1. General description The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of

文件：220.11 Kbytes 页数：11 Pages

NEXPERIA

安世

Dual JK flip-flop Rev. 9 ??18 November 2011

文件：108.35 Kbytes 页数：14 Pages

恩XP

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 页数：5 Pages

PHI

飞利浦

Dual JK flip-flop

文件：684.9 Kbytes 页数：13 Pages

NEXPERIA

安世

Dual JK flip-flop

General description\nThe HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchr

恩XP

Dual JK flip-flop

The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (C • Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• Specified from -40 ºC to +85 ºC\n• Complies with JEDEC standard JESD 13-B;

Nexperia

安世

Dual JK flip-flop

The HEF4027B-Q100 is an edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-dir • Automotive product qualification in accordance with AEC-Q100 (Grade 3)• Specified from -40°C to +85°C\n\n• Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• ESD protection:• MIL-STD-833, method 3015 exceeds 2000V\n• HBM JESD22-A1;

Nexperia

安世

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16SO

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